TI TPS7133QPWRG4
January 15, 2018 | Author: Anonymous | Category: N/A
Short Description
Download TI TPS7133QPWRG4...
Description
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
D D D D D D D D
D OR P PACKAGE (TOP VIEW)
Available in 5-V, 4.85-V, and 3.3-V Fixed-Output and Adjustable Versions Very Low-Dropout Voltage . . . Maximum of 32 mV at IO = 100 mA (TPS7150) Very Low Quiescent Current – Independent of Load . . . 285 µA Typ Extremely Low Sleep-State Current 0.5 µA Max 2% Tolerance Over Specified Conditions For Fixed-Output Versions Output Current Range of 0 mA to 500 mA TSSOP Package Option Offers Reduced Component Height for Space-Critical Applications Power-Good (PG) Status Output
GND EN IN IN
8
2
7
3
6
4
5
PG SENSE†/FB‡ OUT OUT
PW PACKAGE (TOP VIEW)
GND GND GND NC NC EN NC IN IN IN
description The TPS71xx integrated circuits are a family of micropower low-dropout (LDO) voltage regulators. An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance is achieved by replacing the typical pnp pass transistor with a PMOS device.
1
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
PG NC NC FB‡ NC SENSE† OUT OUT NC NC
NC – No internal connection † SENSE – Fixed voltage options only (TPS7133, TPS7148, and TPS7150) ‡ FB – Adjustable version only (TPS7101)
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (maximum of 32 mV at an output current of 100 mA for the TPS7150) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and remains independent of output loading (typically 285 µA over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems. The LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 µA maximum at TJ = 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
description (continued) 0.25 TA = 25°C
Dropout Voltage – V
0.2
0.15
TPS7133 TPS7148
0.1 TPS7150 0.05
0 0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 IO – Output Current – A
Figure 1. Dropout Voltage Versus Output Current Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery indicator. The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in PDIP (8 pin), SO (8 pin), and TSSOP (20-pin) packages. The TSSOP has a maximum height of 1,2 mm. AVAILABLE OPTIONS
TJ
OUTPUT VOLTAGE (V) MIN
– 40°C to 125°C
TYP
MAX
PACKAGED DEVICES SMALL OUTLINE (D)
PLASTIC DIP (P)
TSSOP (PW)
CHIP FORM (Y)
4.9
5
5.1
TPS7150QD
TPS7150QP
TPS7150QPW
TPS7150Y
4.75
4.85
4.95
TPS7148QD
TPS7148QP
TPS7148QPW
TPS7148Y
3.3 3.37 Adjustable† 1.2 V to 9.75 V
TPS7133QD
TPS7133QP
TPS7133QPW
TPS7133Y
TPS7101QD
TPS7101QP
TPS7101QPW
TPS7101Y
3.23
† The D and PW packages are available taped and reeled. Add R suffix to device type (e.g., TPS7150QDR). The TPS7101Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS71xx† 8
VI
IN
PG
9
PG
15 IN
SENSE
IN
OUT
10 0.1 µF
20
6 OUT
EN
14
VO
13 +
GND 1
2
3
CO ‡ 10 µF
CSR
† TPS7133, TPS7148, TPS7150 (fixed-voltage options) ‡ Capacitor selection is nontrivial. See application information section for details.
Figure 2. Typical Application Configuration
TPS71xx chip information These chips, when properly assembled, display characteristics similar to the TPS71xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (5)
(5) (4)
(6)
IN EN
(3) (2)
(6) TPS71xx
(4) (7)
SENSE§ FB¶ OUT PG
(1) (7)
GND CHIP THICKNESS: 15 MILS TYPICAL
80
BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. (3)
(1) (2)
§ SENSE – Fixed voltage options only (TPS7133, TPS7148, and TPS7150) ¶ FB – Adjustable version only (TPS7101) NOTE A: For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to SENSE-pin connection discussion in the Applications Information section of this data sheet.
92
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
functional block diagram IN
RESISTOR DIVIDER OPTIONS †
†
EN
† PG
_
DEVICE
R1
R2
UNIT
TPS7101 TPS7133 TPS7148 TPS7150
0 420 726 756
∞ 233 233 233
Ω kΩ kΩ kΩ
NOTE A: Resistors are nominal values only.
+
OUT COMPONENT COUNT 1.12 V
SENSE‡ /FB
+ _
R1
Vref = 1.178 V
MOS transistors Bilpolar transistors Diodes Capacitors Resistors
464 41 4 17 76
R2
GND † Switch positions are shown with EN low (active). ‡ For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to SENSE-pin connection discussion in Applications Information section.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§ Input voltage range¶, VI, PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 11 V Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2 Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C § Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ¶ All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Figure 3)# PACKAGE
TA ≤ 25°C POWER RATING
DERATING FACTOR ABOVE TA = 25°C
TA = 70°C POWER RATING
TA = 125°C POWER RATING
D P PW||
725 mW 1175 mW 700 mW
5.8 mW/ mW/°C C 9.4 mW/°C 5.6 mW/°C
464 mW 752 mW 448 mW
145 mW 235 mW 140 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Figure 4)# PACKAGE
TC ≤ 25°C POWER RATING
DERATING FACTOR ABOVE TC = 25°C
TC = 70°C POWER RATING
TC = 125°C POWER RATING
D P PW||
2188 mW 2738 mW 4025 mW
17.5 mW/°C 21 9 mW/°C 21.9 32.2 mW/°C
1400 mW 1752 mW 2576 mW
438 mW 548 mW 805 mW
# Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section. || Refer to Thermal Information section for detailed power dissipation considerations when using the TSSOP packages.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
DISSIPATION DERATING CURVE† vs FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE† vs CASE TEMPERATURE 4800 PD – Maximum Continuous Dissipation – mW
PD – Maximum Continuous Dissipation – mW
1400 1200 P Package RθJA = 106°C/W
1000 800
D Package RθJA = 172°C/W
600 400 PW and PWP Package RθJA = 178°C/W
200 0 25
50
75
100
125
150
4400 PW Package RθJC = 31°C/W
4000 3600
P Package RθJC = 46°C/W
3200 2800 2400 2000 1600 1200 800 D Package RθJC = 57°C/W
400 0 25
TA – Free-Air Temperature – °C
50
75
125
100
150
TC – Case Temperature – °C
Figure 3
Figure 4
† Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C. For guidelines on maintaining junction temperature within recommended operating range, see the Thermal Information section.
recommended operating conditions
Input voltage voltage, VI‡
MIN
MAX
TPS7101Q
2.5
10
TPS7133Q
3.77
10
TPS7148Q
5.2
10
TPS7150Q
5.33
10
High-level input voltage at EN, VIH
2
Low-level input voltage at EN, VIL Output current range, IO
0
UNIT
V
V 0.5
V
500
mA
Operating virtual junction temperature range, TJ – 40 125 °C ‡ Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) Because the TPS7101 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for calculating VDO from rDS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the recommended input voltage range for the TPS7101.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE/FB shorted to OUT (unless otherwise noted) TEST CONDITIONS‡
PARAMETER
TJ
TPS7101Q, TPS7133Q TPS7148Q, TPS7150Q MIN
Ground current (active mode)
EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA
VI = VO + 1 V,
Input current (standby mode)
EN = VI,
2 7 V ≤ VI ≤ 10 V 2.7
Output current limit
VO = 0 0,
VI = 10 V
Pass-element leakage g current in standby y mode
EN = VI,
2 7 V ≤ VI ≤ 10 V 2.7
PG leakage current
Normal operation, operation
VPG = 10 V
Output voltage temperature coefficient
25°C
EN logic low (active mode)
350
25°C
0.5
– 40°C to 125°C
2
25°C
1.2
– 40°C to 125°C
2 2
25°C
0.5
– 40°C to 125°C
1
25°C
0.02
– 40°C to 125°C
0.5 0.5
– 40°C to 125°C
61
75
– 40°C to 125°C
6 V ≤ VI ≤ 10 V 2 7 V ≤ VI ≤ 10 V 2.7
2
0 V ≤ VI ≤ 10 V
0 V ≤ VI ≤ 10 V
25°C
0.5
– 40°C to 125°C
0.5 50 – 0.5
0.5
– 40°C to 125°C
– 0.5
0.5 2.05
– 40°C to 125°C IPG = 300 µA
IPG = 300 µA
25°C – 40°C to 125°C
µA A µA µA ppm/°C
2.5 2.5
1.06
V mV
25°C 25°C
µA
V
2.7
25°C
UNIT
°C
165 2.5 V ≤ VI ≤ 6 V
Minimum VI for active pass element Minimum VI for valid PG
285
460
EN hysteresis voltage EN input current
MAX
– 40°C to 125°C
Thermal shutdown junction temperature EN logic high (standby mode)
TYP
1.5 1.9
µA V V
† CSR (compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS7101 electrical characteristics at IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, FB shorted to OUT at device leads (unless otherwise noted) TEST CONDITIONS‡
PARAMETER Reference voltage (measured at FB with OUT connected to FB)
VI = 3.5 V, 2.5 V ≤ VI ≤ 10 V, See Note 1
IO = 10 mA 5 mA ≤ IO ≤ 500 mA,
Reference voltage temperature coefficient
Pass-element series resistance (see Note 2)
Input regulation
Output regulation
VI = 2 2.4 4V V,
50 µA ≤ IO ≤ 150 mA
VI = 2 2.4 4V V,
150 mA ≤ IO ≤ 500 mA
25°C – 40°C to 125°C
TYP
MAX
1.178 1.143
1.213
– 40°C to 125°C
61
75
25°C
0.7
1
0.83
1.3
0.52
0.85
– 40°C to 125°C – 40°C to 125°C
1.3
25°C
50 µA ≤ IO ≤ 500 mA
25°C
0.32
50 µA ≤ IO ≤ 500 mA
25°C
0.23
VI = 2.5 V to 10 V,, See Note 1
50 µ µA ≤ IO ≤ 500 mA,,
25°C
18
– 40°C to 125°C
25
IO = 5 mA to 500 mA,, See Note 1
2.5 V ≤ VI ≤ 10 V,,
IO = 50 µA µ to 500 mA,, See Note 1
2.5 V ≤ VI ≤ 10 V,,
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz H ≤ f ≤ 100 kHz, kH CSR† = 1 Ω
25°C
14
– 40°C to 125°C
25
25°C
22
– 40°C to 125°C
54
25°C
48
– 40°C to 125°C
44
25°C
45
– 40°C to 125°C
44
25°C
95
25°C
89
CO = 100 µF
25°C
74
Measured at VFB VI = 2 2.13 13 V
FB input current
1.101 12
25°C
0.1
– 40°C to 125°C – 10 – 20
mV
µVrms
0.1
V mV
0.4 0.4
25°C
mV
µV/√Hz
1.145
25°C
– 40°C to 125°C
mV
dB
54
CO = 10 µF
– 40°C to 125°C
Ω
59
CO = 4.7 µF
VFB voltage decreasing from above VPG
ppm/°C
0.85
2
PG hysteresis voltage§
IPG = 400 µA µA,
– 40°C to 125°C
25°C
PG trip-threshold voltage§
V
1
25°C
VI = 3.9 V, VI = 5.9 V,
f = 120 Hz
UNIT V
50 µA ≤ IO ≤ 500 mA
IO = 500 mA,, See Note 1
PG output low voltage§
TPS7101Q MIN
VI = 2 2.9 9V V,
IO = 50 µA Ripple rejection
TJ
10 20
V nA
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS7133 electrical characteristics at IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡
PARAMETER Output voltage
VI = 4.3 V, 4.3 V ≤ VI ≤ 10 V,
IO = 10 mA 5 mA ≤ IO ≤ 500 mA
IO = 10 mA mA,
VI = 3 3.23 23 V
mA IO = 100 mA,
23 V VI = 3 3.23
IO = 500 mA, mA
VI = 3 3.23 23 V
Pass element series resistance Pass-element
( (3.23 V – VO))/IO, IO = 500 mA
VI = 3.23 V,,
Input regulation
VI = 4.3 4 3 V to 10 V, V
50 µA ≤ IO ≤ 500 mA
IO = 5 mA to 500 mA, mA
4 3 V ≤ VI ≤ 10 V 4.3
IO = 50 µA to 500 mA mA,
4 3 V ≤ VI ≤ 10 V 4.3
Dropout voltage
Output regulation
IO = 50 µA Ripple rejection
f = 120 Hz IO = 500 mA
Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz H ≤ f ≤ 100 kHz, kH CSR† = 1 Ω
PG trip-threshold voltage
TJ 25°C – 40°C to 125°C 25°C
3.37 4.5
7
47
60
– 40°C to 125°C
80
25°C
235
– 40°C to 125°C
mV
300
0.47
0.6
– 40°C to 125°C
0.8
25°C
20
– 40°C to 125°C
27
25°C
21
– 40°C to 125°C
38 75
25°C
30
– 40°C to 125°C
60 120
25°C
43
– 40°C to 125°C
40
25°C
39
– 40°C to 125°C
36
Ω mV mV mV
54 dB
49
CO = 4.7 µF
25°C
274
CO = 10 µF
25°C
228
CO = 100 µF
25°C
159 2.868
µV/√Hz µVrms
3
25°C
35
25°C
0.22
– 40°C to 125°C
V
400
25°C
– 40°C to 125°C
UNIT
8
25°C
2
VI = 2 2.8 8V
MAX
3.3 3.23
25°C
VO voltage decreasing from above VPG
IPG = 1 mA mA,
TYP
– 40°C to 125°C
PG hysteresis voltage PG output low voltage
TPS7133Q MIN
V mV
0.4 0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS7148 electrical characteristics at IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡
PARAMETER Output voltage
VI = 5.85 V, 5.85 V ≤ VI ≤ 10 V,
IO = 10 mA 5 mA ≤ IO ≤ 500 mA
IO = 10 mA mA,
VI = 4 4.75 75 V
mA IO = 100 mA,
75 V VI = 4 4.75
IO = 500 mA, mA
VI = 4 4.75 75 V
Pass element series resistance Pass-element
( (4.75 V – VO))/IO, IO = 500 mA
VI = 4.75 V,,
Input regulation
VI = 5 5.85 85 V to 10 V V,
50 µA ≤ IO ≤ 500 mA
IO = 5 mA to 500 mA, mA
5 85 V ≤ VI ≤ 10 V 5.85
IO = 50 µA to 500 mA mA,
5 85 V ≤ VI ≤ 10 V 5.85
Dropout voltage
IO = 50 µA f = 120 Hz IO = 500 mA Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz H ≤ f ≤ 100 kHz, kH CSR† = 1 Ω
PG trip-threshold voltage
25°C – 40°C to 125°C 25°C
4.95 2.9
6
30
37
– 40°C to 125°C
54
25°C
150
180
0.32
0.35
– 40°C to 125°C
0.52
25°C
27
– 40°C to 125°C
37
25°C
12
– 40°C to 125°C
42 80
25°C
42
– 40°C to 125°C
60 130
25°C
42
– 40°C to 125°C
39
25°C
39
– 40°C to 125°C
35
mV
Ω mV mV mV
53 dB
50
CO = 4.7 µF
25°C
410
CO = 10 µF
25°C
328
CO = 100 µF
25°C
212 4.5
µV/√Hz µVrms
4.7
25°C
50
25°C
0.2
– 40°C to 125°C
V
250
25°C
– 40°C to 125°C
UNIT
8
25°C
2
12 V VI = 4 4.12
MAX
4.85 4.75
25°C
VO voltage decreasing from above VPG
1 2 mA, mA IPG = 1.2
TYP
– 40°C to 125°C
PG hysteresis voltage PG output low voltage
TPS7148Q MIN
– 40°C to 125°C
Output regulation
Ripple rejection
TJ
V mV
0.4 0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS7150 electrical characteristics at IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, SENSE shorted to OUT (unless otherwise noted) TEST CONDITIONS‡
PARAMETER Output voltage
VI = 6 V, 6 V ≤ VI ≤ 10 V,
IO = 10 mA 5 mA ≤ IO ≤ 500 mA
IO = 10 mA mA,
VI = 4 4.88 88 V
mA IO = 100 mA,
88 V VI = 4 4.88
IO = 500 mA, mA
VI = 4 4.88 88 V
Pass element series resistance Pass-element
( (4.88 V – VO))/IO, IO = 500 mA
VI = 4.88 V,,
Input regulation
VI = 6 V to 10 V, V
50 µA ≤ IO ≤ 500 mA
IO = 5 mA to 500 mA, mA
6 V ≤ VI ≤ 10 V
IO = 50 µA to 500 mA mA,
6 V ≤ VI ≤ 10 V
Dropout voltage
IO = 50 µA f = 120 Hz IO = 500 mA Output noise-spectral density
f = 120 Hz
Output noise voltage
10 Hz H ≤ f ≤ 100 kHz, kH CSR† = 1 Ω
PG trip-threshold voltage
25°C – 40°C to 125°C 25°C
5.1 2.9
6
27
32
– 40°C to 125°C
47
25°C
146
170
0.29
0.32
– 40°C to 125°C
0.47
25°C
25
– 40°C to 125°C
32
25°C
30
– 40°C to 125°C
45 86
25°C
45
– 40°C to 125°C
65 140
25°C
45
– 40°C to 125°C
40
25°C
42
– 40°C to 125°C
36
mV
Ω mV mV mV
55 dB
52
CO = 4.7 µF
25°C
430
CO = 10 µF
25°C
345
CO = 100 µF
25°C
220 4.55
µV/√Hz µVrms
4.75
25°C
53
25°C
0.2
– 40°C to 125°C
V
230
25°C
– 40°C to 125°C
UNIT
8
25°C
2
VI = 4 4.25 25 V
MAX
5 4.9
25°C
VO voltage decreasing from above VPG
IPG = 1.2 1 2 mA, mA
TYP
– 40°C to 125°C
PG hysteresis voltage PG output low voltage
TPS7150Q MIN
– 40°C to 125°C
Output regulation
Ripple rejection
TJ
V mV
0.4 0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE/FB shorted to OUT (unless otherwise noted) TEST CONDITIONS‡
PARAMETER
TPS7101Y, TPS7133Y TPS7148Y, TPS7150Y MIN
Ground current (active mode)
EN ≤ 0.5 V, 0 mA ≤ IO ≤ 500 mA
VI = VO + 1 V,
Output current limit
VO = 0,
VI = 10 V
PG leakage current
Normal operation,
VPG = 10 V
TYP
EN hysteresis voltage Minimum VI for active pass element Minimum VI for valid PG
IPG = 300 µA
TEST CONDITIONS‡
PARAMETER Reference voltage (measured at FB with OUT connected to FB)
µA
285
Thermal shutdown junction temperature
1.2
A
0.02
µA
165
°C
50
mV
2.05
V
1.06
V
TPS7101Y MIN
UNIT
MAX
TYP
MAX
VI = 3.5 V,
IO = 10 mA
VI = 2.4 V, VI = 2.4 V,
50 µA ≤ IO ≤ 150 mA 150 mA ≤ IO ≤ 500 mA
0.83
VI = 2.9 V, VI = 3.9 V,
50 µA ≤ IO ≤ 500 mA
0.52
50 µA ≤ IO ≤ 500 mA
0.32
VI = 5.9 V, VI = 2.5 V to 10 V, See Note 1
50 µA ≤ IO ≤ 500 mA
0.23
50 µA ≤ IO ≤ 500 mA,
18
mV
2.5 V ≤ VI ≤ 10 V, See Note 1
IO = 5 mA to 500 mA,
14
mV
2.5 V ≤ VI ≤ 10 V, See Note 1
IO = 50 µA to 500 mA,
22
mV
Ripple rejection
VI = 3.5 V, IO = 50 µA
f = 120 Hz,
Output noise-spectral density
VI = 3.5 V,
f = 120 Hz
Pass-element series resistance (see Note 2)
Input regulation
Output regulation
Output noise voltage
VI = 3.5 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω
1.178
UNIT V
0.7 Ω
59
dB
2
µV/√Hz
CO = 4.7 µF
95
CO = 10 µF
89
CO = 100 µF
74
µVrms
PG hysteresis voltage§
VI = 3.5 V,
Measured at VFB
12
mV
PG output low voltage§
VI = 2.13 V,
IPG = 400 µA
0.1
V
FB input current 0.1 nA VI = 3.5 V VI = 3.5 V † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately. § Output voltage programmed to 2.5 V with closed-loop configuration (see application information). NOTES: 1. When VI < 2.9 V and IO > 150 mA simultaneously, pass element rDS(on) increases (see Figure 27) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range. 2. To calculate dropout voltage, use equation: VDO = IO ⋅ rDS(on) rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other programmed values, refer to Figure 26.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) (continued) TEST CONDITIONS‡
PARAMETER Output voltage
TPS7133Y MIN
TYP
MAX
VI = 4.3 V, VI = 3.23 V,
IO = 10 mA IO = 10 mA
0.02
VI = 3.23 V, VI = 3.23 V,
IO = 100 mA IO = 500 mA
235
(3.23 V – VO)/IO, IO = 500 mA
VI = 3.23 V,
0.47
4.3 V ≤ VI ≤ 10 V,
IO = 5 mA to 500 mA IO = 50 µA to 500 mA
21
mV
4.3 V ≤ VI ≤ 10 V,
30
mV
Ripple rejection
VI = 4.3 V,, f = 120 Hz
IO = 50 µA IO = 500 mA
54
Output noise-spectral density
VI = 4.3 V,
f = 120 Hz
Output noise voltage
VI = 4.3 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω
Dropout voltage
Pass-element series resistance Output regulation
PG hysteresis voltage
VI = 4.3 V
PG output low voltage
VI = 2.8 V,
Output voltage
V mV
47
Ω
dB
49
µV/√Hz
2
CO = 4.7 µF
274
CO = 10 µF
228
CO = 100 µF
159
IPG = 1 mA
0.22
µVrms
35
TEST CONDITIONS‡
PARAMETER
3.3
UNIT
mV V
TPS7148Y MIN
TYP
UNIT
VI = 5.85 V, VI = 4.75 V,
IO = 10 mA IO = 10 mA
VI = 4.75 V, VI = 4.75 V,
IO = 100 mA IO = 500 mA
150
(4.75 V – VO)/IO, IO = 500 mA
VI = 4.75 V,
0.32
5.85 V ≤ VI ≤ 10 V,
12
mV
5.85 V ≤ VI ≤ 10 V,
IO = 5 mA to 500 mA IO = 50 µA to 500 mA
42
mV
Ripple rejection
VI = 5.85 V,, f = 120 Hz
IO = 50 µA IO = 500 mA
53
Output noise-spectral density
VI = 5.85 V,
f = 120 Hz
Dropout voltage
Pass-element series resistance Output regulation
Output noise voltage
VI = 5.85 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω
PG hysteresis voltage
VI = 5.85 V
4.85
MAX
V
0.08 30
50 2
CO = 4.7 µF
410
CO = 10 µF
328
CO = 100 µF
212 50
mV
Ω
dB µV/√Hz µVrms
mV
VI = 4.12 V, IPG = 1.2 mA 0.2 0.4 V PG output low voltage † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
electrical characteristics at IO = 10 mA, EN = 0 V, CO = 4.7 µF/CSR† = 1 Ω, TJ = 25°C, SENSE shorted to OUT (unless otherwise noted) (continued) TEST CONDITIONS‡
PARAMETER Output voltage
TPS7150Y MIN
TYP
UNIT
VI = 6 V, VI = 4.88 V,
IO = 10 mA IO = 10 mA
0.13
VI = 4.88 V, VI = 4.88 V,
IO = 100 mA IO = 500 µA
146
(4.88 V – VO)/IO, IO = 500 mA
VI = 4.88 V,
0.29
6 V ≤ VI ≤ 10 V,
IO = 5 mA to 500 mA IO = 50 µA to 500 mA
30
mV
6 V ≤ VI ≤ 10 V,
45
mV
Ripple rejection
VI = 6 V,, f = 120 Hz
IO = 50 µA IO = 500 mA
55
Output noise-spectral density
VI = 6 V,
f = 120 Hz
Output noise voltage
VI = 6 V, 10 Hz ≤ f ≤ 100 kHz, CSR† = 1 Ω
Dropout voltage
Pass-element series resistance Output regulation
PG hysteresis voltage
5
MAX
27
52 2
CO = 4.7 µF
430
CO = 10 µF
345
CO = 100 µF
220 53
VI = 6 V
V mV
Ω
dB µV/√Hz µVrms
mV
VI = 4.25 V, 0.2 V PG output low voltage PG = 1.2 mA † CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. ‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs Output current
5
vs Input voltage
6
vs Free-air temperature
7
vs Output current
8
Change in dropout voltage
vs Free-air temperature
9
∆VO VO
Change in output voltage
vs Free-air temperature
10
Output voltage
vs Input voltage
11
∆VO
Change in output voltage
vs Input voltage
12
IQ
Quiescent current
VDO ∆VDO
Dropout voltage
13 VO
Output voltage
vs Output current
14 15 16 17
Ripple rejection
vs Frequency
18 19 20 21 22
Output spectral noise density
vs Frequency
rDS(on)
Pass-element resistance
vs Input voltage
25
R
Divider resistance
vs Free-air temperature
26
II(SENSE)
SENSE pin current
vs Free-air temperature
27
FB leakage current
vs Free-air temperature
28
Minimum input voltage for active-pass element
vs Free-air temperature
29
Minimum input voltage for valid PG
vs Free-air temperature
30
Input current (EN)
vs Free-air temperature
31
23 24
VI II(EN)
Output voltage response from Enable (EN)
14
32
VPG
Power-good (PG) voltage
vs Output voltage
CSR
Compensation series resistance
vs Output current
CSR
Compensation series resistance
vs Added ceramic capacitance
CSR
Compensation series resistance
vs Output current
CSR
Compensation series resistance
vs Added ceramic capacitance
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33 34 35 36 37 38 39 40 41
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs OUTPUT CURRENT
QUIESCENT CURRENT vs INPUT VOLTAGE
355
400
345
350
335
TPS71xx, VI = 10 V
I Q – Quiescent Current – µ A
I Q – Quiescent Current – µ A
TA = 25°C RL = 10 Ω
TA = 25°C
325 315 305 295
TPS7150, VI = 6 V
285
TPS7133
300
TPS7148 250
TPS7150
200 TPS7101 With VO Programmed to 2.5 V
150 100
TPS7148, VI = 5.85 V 275
50
TPS7133, VI = 4.3 V
265
0
50 100 150 200 250 300 350 400 450 500
0
0
1
2
3
IO – Output Current – mA
4
5
6
7
8
9
10
VI – Input Voltage – V
Figure 5
Figure 6
TPS7148Q
QUIESCENT CURRENT vs FREE-AIR TEMPERATURE
DROPOUT VOLTAGE vs OUTPUT CURRENT
400
0.3 TA = 25°C 0.25
350
TPS7133 Dropout Voltage – V
I Q – Quiesent Current – µ A
VI = VO(nom) + 1 V IO = 10 mA
300
250
0.2
0.15
TPS7148
0.1 TPS7150
200
150 – 50
0.05
0 – 25
0 25 50 75 100 TA – Free-Air Temperature – °C
125
0
50 100 150 200 250 300 350 400 450 500 IO – Output Current – mA
Figure 8
Figure 7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS CHANGE IN DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE
CHANGE IN OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
10
20 IO = 100 mA ∆ VO – Change in Output Voltage – mV
Change in Dropout Voltage – mV
8 6 4 2 0 –2 –4 –6 –8 – 10 – 50
– 25
0
25
50
75
100
VI = VO(nom) + 1 V IO = 10 mA
15 10 5 0 –5 – 10 – 15
– 20 – 50
125
– 25
TA – Free-Air Temperature – °C
0
Figure 9
20
TA = 25°C RL = 10 Ω
∆VO– Change In Output Voltage – mV
TPS7150
VO – Output Voltage – V
5 TPS7148 4
3 TPS7133 TPS7101 With VO Programmed to 2.5 V
1
0
1
2
3
4
100
125
5
6
7
8
9
10
TA = 25°C RL = 10 Ω
15 10
TPS7150
5
TPS7148 0 –5
TPS7133
– 10 – 15 – 20 4
VI – Input Voltage – V
Figure 11
16
75
CHANGE IN OUTPUT VOLTAGE vs INPUT VOLTAGE
6
0
50
Figure 10
OUTPUT VOLTAGE vs INPUT VOLTAGE
2
25
TA – Free-Air Temperature – °C
5
8 6 7 VI – Input Voltage – V
Figure 12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
10
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS TPS7101Q
TPS7133Q
OUTPUT VOLTAGE vs OUTPUT CURRENT
OUTPUT VOLTAGE vs OUTPUT CURRENT
2.52
3.34 TA = 25°C VO Programmed to 2.5 V
TA = 25°C 3.33
2.51
VO – Output Voltage – V
VO – Output Voltage – V
2.515
2.505 2.5
VI = 3.5 V
2.495
VI = 10 V
3.32 3.31
3.28
2.485
3.27
0
100
200
400
300
VI = 4.3 V
3.29
2.49
2.48
VI = 10 V
3.3
3.26
500
0
400 200 300 IO – Output Current – mA
100
IO – Output Current – mA
Figure 13
Figure 14
TPS7148Q
TPS7150Q
OUTPUT VOLTAGE vs OUTPUT CURRENT
OUTPUT VOLTAGE vs OUTPUT CURRENT
4.92
5.06 TA = 25°C
5.05
4.9
5.04
4.89
5.03
VO – Output Voltage – V
VO – Output Voltage – V
4.91
4.88 4.87 VI = 5.85 V
4.86 4.85
VI = 10 V
4.84 4.83
TA = 25°C
5.02 5.01
VI = 6 V
5 4.99
VI = 10 V
4.98 4.97
4.82
4.96
4.81
4.95
4.8
500
0
100
200
300
400
500
4.94
0
IO – Output Current – mA
100
300 200 400 IO – Output Current – mA
500
Figure 16
Figure 15
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TPS7101Q
TPS7133Q
RIPPLE REJECTION vs FREQUENCY
RIPPLE REJECTION vs FREQUENCY
70
70
60
60
40 30 20 10 0 10
RL = 500 Ω
TA = 25°C VI = 3.5 V
RL = 100 kΩ
50
RL = 100 kΩ
50
Ripple Rejection – dB
Ripple Rejection – dB
TYPICAL CHARACTERISTICS
CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance VO Programmed to 2.5 V
40 30
RL = 500 Ω
20 RL = 10 Ω TA = 25°C VI = 3.5 V
10
CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance
0
RL = 10 Ω 100
1K
10K
100K
1M
– 10 10
10M
100
1k
10 k
Figure 17 TPS7148Q
TPS7150Q
RIPPLE REJECTION vs FREQUENCY
RIPPLE REJECTION vs FREQUENCY
Ripple Rejection – dB
Ripple Rejection – dB
RL = 100 kΩ RL = 10 Ω
30 RL = 500 Ω
20
TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance 100
1k
10 k
40
1M
10 M
RL = 10 Ω
30
RL = 500 Ω
20 10
100 k
RL = 100 kΩ
50
TA = 25°C VI = 3.5 V CO = 4.7 µF (CSR = 1 Ω) No Input Capacitance
0 10
f – Frequency – Hz
100
1k
10 k
Figure 20
POST OFFICE BOX 655303
100 k
f – Frequency – Hz
Figure 19
18
10 M
60
50
– 10 10
1M
70
60
0
10 M
Figure 18
70
10
1M
f – Frequency – Hz
f – Frequency – Hz
40
100 k
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS TPS7101Q
TPS7133Q
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
TA = 25°C No Input Capacitance VI = 3.5 V VO Programmed to 2.5 V CO = 4.7 µF (CSR = 1 Ω)
1 CO = 10 µF (CSR = 1 Ω)
0.1
10 Output Spectral Noise Density – µV/ Hz
Output Spectral Noise Density – µV/ Hz
10
CO = 100 µF (CSR = 1 Ω) 0.01 10
102
103
104
TA = 25°C No Input Capacitance VI = 4.3 V CO = 10 µF (CSR = 1 Ω)
1
CO = 4.7 µF (CSR = 1 Ω) CO = 100 µF (CSR = 1 Ω)
0.1
0.01 10
105
102
f – Frequency – Hz
f – Frequency – Hz
Figure 21
Figure 22
TPS7148Q
104
105
TPS7150Q
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
10
10 TA = 25°C No Input Capacitance VI = 5.85 V CO = 10 µF (CSR = 1 Ω)
1
CO = 4.7 µF (CSR = 1 Ω)
0.1
CO = 100 µF (CSR = 1 Ω)
Output Spectral Noise Density – µV/ Hz
Output Spectral Noise Density – µV/ Hz
103
CO = 10 µF (CSR = 1 Ω) CO = 4.7 µF (CSR = 1 Ω) 1 TA = 25°C No Input Capacitance VI = 6 V
0.1
CO = 100 µF (CSR = 1 Ω) 0.01 10
100
1k 10 k f – Frequency – Hz
100 k
0.01 10
Figure 23
100
1k 10 k f – Frequency – Hz
100 k
Figure 24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS PASS-ELEMENT RESISTANCE vs INPUT VOLTAGE
DIVIDER RESISTANCE vs FREE-AIR TEMPERATURE 1.2
TA = 25°C VI(FB) = 1.12 V
1
0.8 IO = 500 mA
0.7 0.6 0.5
VI = VO(nom) + 1 V VI(sense) = VO(nom)
1.1
0.9
R – Divider Resistance – M Ω
rDS(on) – Pass-Element Resistance – Ω
1.1
IO = 100 mA
0.4
TPS7150 1 TPS7148 0.9 0.8 0.7 TPS7133
0.6
0.3 0.5
0.2 0.1 3
2
4
6 8 5 7 VI – Input Voltage – V
9
0.4 – 50
10
– 25
0
100
125
100
125
ADJUSTABLE VERSION FB LEAKAGE CURRENT vs FREE-AIR TEMPERATURE
6
0.6 VI = VO(nom) + 1 V VI(sense) = VO(nom)
VFB = 2.5 V 0.5
5.6
FB Leakage Current – nA
I I(sense) – Sense Pin Current – µ A
75
Figure 26
FIXED-OUTPUT VERSIONS SENSE PIN CURRENT vs FREE-AIR TEMPERATURE
5.4 5.2 5 4.8
4.4 – 50
0.4
0.3
0.2
0.1
4.6
– 25
0
25
50
75
100
125
0 – 50
TA – Free-Air Temperature – °C
– 25
0
25
Figure 28
POST OFFICE BOX 655303
50
75
TA – Free-Air Temperature – °C
Figure 27
20
50
TA – Free-Air Temperature – °C
Figure 25
5.8
25
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS MINIMUM INPUT VOLTAGE FOR ACTIVE PASS ELEMENT vs FREE-AIR TEMPERATURE
VI – Minimum Input Voltage – V
2.09
1.1 RL = 500 Ω VI – Minimum Input Voltage – V
2.1
MINIMUM INPUT VOLTAGE FOR VALID POWER GOOD (PG) vs FREE-AIR TEMPERATURE
2.08 2.07 2.06 2.05 2.04
ÁÁ ÁÁ
1.08
1.07
ÁÁ ÁÁ
2.03 2.02 2.01 – 25
0 25 50 75 100 TA – Free-Air Temperature – °C
1.06
1.05 – 50
125
– 25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
Figure 29
Figure 30 EN INPUT CURRENT vs FREE-AIR TEMPERATURE
100 90
VI = VI(EN) = 10 V
80 I I(EN) – Input Current – nA
2 – 50
1.09
70 60 50 40 30 20 10 0 – 40 – 20
0 20 40 60 80 100 120 140 TA – Free-Air Temperature – °C
Figure 31
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS
VO – Output Voltage – V
OUTPUT VOLTAGE RESPONSE FROM ENABLE (EN) VO(nom)
TA = 25°C RL = 500 Ω CO = 4.7 µF (ESR = 1Ω) No Input Capacitance
4 2 0 –2
0
20
40
60
80 100 120 140
Time – µs
Figure 32 POWER-GOOD (PG) VOLTAGE vs OUTPUT VOLTAGE 6
VPG – Power-Good (PG) Voltage – V
TA = 25°C PG Pulled Up to 5 V With 5 kΩ 5
4
3
ÁÁ ÁÁ
2
1
0 93
94
95
96
97
98
VO – Output Voltage (VO as a percent of VO(nom)) – %
Figure 33
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
EN Voltage – V
6
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT 100
100
VI = VO(nom) + 1 V No Input Capacitance CO = 4.7 µF No Added Ceramic Capacitance TA = 25°C
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT
Region of Instability
10
1
Region of Instability
VI = VO(nom) + 1 V No Input Capacitance CO = 4.7 µF + 0.5 µF of Ceramic Capacitance TA = 25°C 10
Region of Instability
1
Region of Instability 0.1
0.1 0
0
50 100 150 200 250 300 350 400 450 500
50 100 150 200 250 300 350 400 450 500 IO – Output Current – mA
IO – Output Current – mA
Figure 34
Figure 35
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE
COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE 100
VI = VO(nom) + 1 V No Input Capacitance IO= 100 mA CO = 4.7 µF TA = 25°C 10
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
Region of Instability
1
Region of Instability 0.1
VI = VO(nom) + 1 V No Input Capacitance IO= 500 mA CO = 4.7 µF TA = 25°C 10
Region of Instability
1
Region of Instability 0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Ceramic Capacitance – µF
1
Ceramic Capacitance – µF
Figure 36
Figure 37
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS TYPICAL REGIONS OF STABILITY†
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE vs OUTPUT CURRENT
Region of Instability
100
VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF No Ceramic Capacitance TA = 25°C
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
10
1
0.2 0.1 0
VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF + 0.5 µF of Added Ceramic Capacitance TA = 25°C
10 Region of Instability
1
0.2 0.1
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
IO – Output Current – mA
IO – Output Current – mA
Figure 38 TYPICAL REGIONS OF STABILITY†
TYPICAL REGIONS OF STABILITY†
COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE
COMPENSATION SERIES RESISTANCE vs ADDED CERAMIC CAPACITANCE 100
VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF IO = 100 mA TA = 25°C
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
Figure 39
10 Region of Instability
1
0.2 0.1
VI = VO(nom) + 1 V No Input Capacitance CO = 10 µF IO = 500 mA TA = 25°C
10 Region of Instability
1
0.2 0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Ceramic Capacitance – µF
Ceramic Capacitance – µF
Figure 40
Figure 41
† CSR values below 0.1 Ω are not recommended.
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
TYPICAL CHARACTERISTICS VI
To Load
IN OUT SENSE EN
+ CO
GND
Ccer†
RL
CSR
† Ceramic capacitor
Figure 42. Test Circuit for Typical Regions of Stability (Figures 34 through 41)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
APPLICATION INFORMATION The TPS71xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good indicator. The TPS71xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the TPS7148 (4.85 V), and the TPS7150 (5 V). The family also offers an adjustable device, the TPS7101 (adjustable from 1.2 V to 9.75 V).
device operation The TPS71xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). Close examination of the data sheets reveals that those devices are typically specified under near no-load conditions; actual operating currents are much higher as evidenced by typical quiescent current versus load current curves. The TPS71xx uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low and invariable over the full load range. The TPS71xx specifications reflect actual performance under load. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS71xx quiescent current remains low even when the regulator drops out, eliminating both problems. Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack before the device drops out, adding crucial talk minutes between charges. The TPS71xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 µA. If the shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output voltage is reestablished in typically 120 µs.
minimum load requirements The TPS71xx family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the regulator. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate.
external capacitor requirements An input capacitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 µF) improves load transient response and noise rejection if the TPS71xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
APPLICATION INFORMATION external capacitor requirements (continued) As with most LDO regulators, the TPS71xx family requires an output capacitor for stability. A 10-µF solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the full load range (see Figure 43). Adding high-frequency ceramic or film capacitors (such as power-supply bypass capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum capacitor is less than 1.2 Ω over temperature. Where component height and/or mounting area is a problem, physically smaller, 10-µF devices can be screened for ESR. Figures 34 through 41 show the stable regions of operation using different values of output capacitance with various values of ceramic load capacitance. In applications with little or no high-frequency bypass capacitance (< 0.2 µF), the output capacitance can be reduced to 4.7 µF, provided ESR is maintained between the values shown in figures 34 through 41. Because minimum capacitor ESR is seldom if ever specified, it may be necessary to add a 0.5-Ω to 1-Ω resistor in series with the capacitor and limit ESR to 1.5 Ω maximum. TPS71xx† 8
VI
9 10 C1 0.1 µF 50 V
6
IN
PG
IN
SENSE
IN
OUT
EN
OUT
20
2
250 kΩ
14
VO
13
GND 1
PG
15
3
+
CO 10 µF
ESR
† TPS7133, TPS7148, TPS7150 (fixed-voltage options)
Figure 43. Typical Application Circuit
programming the TPS7101 adjustable LDO regulator Programming the adjustable regulators is accomplished using an external resistor divider as shown in Figure 44. The equation governing the output voltage is: V
O
ǒ Ǔ
+ Vref @ 1 ) R1 R2
where Vref = reference voltage, 1.178 V typ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y LOW-DROPOUT VOLTAGE REGULATORS SLVS092G – NOVEMBER 1994 – REVISED JANUARY 2003
APPLICATION INFORMATION programming the TPS7101 adjustable LDO regulator (continued) Resistors R1 and R2 should be chosen for approximately 7-µA divider current. A recommended value for R2 is 169 kΩ with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at FB introduce an error. Solving equation 1 for R1 yields a more useful equation for choosing the appropriate resistance: R1
+
ǒ Ǔ V
V
O
ref
* 1 @ R2 OUTPUT VOLTAGE PROGRAMMING GUIDE
TPS7101 VI
PG
IN
0.1 µF
>2.7 V
Power-Good Indicator 250 kΩ
OUT
EN
VO
View more...
Comments
